Pierre-Yves Péneau

Pierre-Yves Péneau

Senior Security Analyst

Riscure B.V.


I am a senior security analyst at Riscure B.V. in the Netherlands. Previously, I was at the French Institute for Computer Science (INRIA), specificaly at the High Security Laboratory. I was in charge of developing a new platform dedicated to fault injection through clock glitches. I received my PhD from the University of Montpellier in October 2018, and my MSc from the Pierre and Marie Curie University (now Sorbonne Universités).

My research interests include fault injection, side-channel attack, embedded systems and computer architecture.

  • Hardware security
  • Fault injection
  • Side channel attack
  • Computer architecture
  • PhD in Computer Science, 2018

    Montpellier University

  • MSc in Computer Science, 2015

    La Sorbonne University

  • BSc in Computer Science, 2013

    Nantes University

Latest experience

Riscure B.V.
Senior Security Analyst
Nov 2021 – Present Delft, Netherlands
French National Institute For Scientific Research
Hardware Security Engineer
Jan 2019 – Sep 2021 Rennes, France
Setting up a new fault injection platform based on clock glitches
French National Centre for Scientific Research
PhD candidate
Oct 2015 – Oct 2018 Montpellier, France
Integration of emerging non-volatile memory technologies in cache hierarchy for improving energy-efficiency

Recent publications

(2020). NOP-Oriented Programming: Should we Care?. In EuroS&PW.

PDF Cite Code Slides

(2019). Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC.

PDF Cite Project


  • Delftechpark 49, Delft, 2628 XJ, The Netherlands
  • Monday-Friday 09:00 to 18:00