Today, intensive efforts to design energy-efficient and high-performance systems-on-chip (SoCs) are underway. Moore’s end in the early 20 th century pushed designers to increase the number of core per processor to continue to improve the performance. As a result, the silicon area occupied by cache memories has increased. The ever smaller technology node also increased the leakage current of CMOS transistors. Thus, the energy consumption of memories represents an increasingly important part in the overall consumption of chips. To reduce this energy consumption, new memory technologies have emerged over the past decade
: non-volatile memories (NVM). These memories have the particularity of having a very low leakage current compared to conventional CMOS technologies. In fact, their use in an architecture would reduce the overall consumption of the cache hierarchy. However, these technologies suffer from higher access latencies than SRAM, higher access energy costs and limited lifetime. Their integration into SoCs requires a continuous research effort. This thesis work aims to evaluate the impact of a change in technology in the cache hierarchy. More specifically, we are interested in the Last-Level Cache (LLC) and we consider the STT-MRAM technology. Our work adopts an architectural point of view in which a modification of the technology is not retained. Then, we try to integrate the different characteristics of the STT-MRAM at architectural level when designing the memory hierarchy. A first study set up an architectural exploration framework for systems containing emerging memories. A second study on architectural optimizations at LLC was conducted to identify opportunities for the integration of STT-MRAM. The goal is to improve energy efficiency while reducing access penalties due to the high latency of this technology.